1. Field of the Invention
Embodiments of the present invention relates generally to clocks and data recovery, and more particularly, to multi-channel delay cell based clocks and data recovery.
2. Background Art
Typically, data is commonly processed in parallel within computers. When transmitting data from one computer to another, however, data is generally sent in serial to save on interconnection pins and to reduce errors in transmission. For example, ten data streams, each within a separate parallel channel, may be processed by a computer. The ten separate data streams may be serialized into a single high speed channel and transmitted to a receiving computer. The receiving computer may then separate the ten data streams back into parallel channels for further processing. Unfortunately, if the clock cycle of the receiving computer is not in phase with the serialized data, errors in reading the serialized data can occur.
In high speed serialized data transmission, a high speed clock signal is not normally provided between the two computers due to difficulties in maintaining a fixed timing relationship between the high speed clock signal and the serialized data. If a high speed clock signal is transmitted to the receiving computer, the high speed clock signal can jitter in transmission. Jitter refers to timing errors. Jitter may be caused by electromagnetic interference (EMI), crosstalk with other signals, or any other noise. When a high speed clock signal jitters out of phase with the serialized data, the receiving computer attempting to separate the serialized data into parallel channels based on the high speed clock cycle may encounter errors or data corruption.
Therefore, there is a need to restore parallel data from transmitted serialized data using a clock signal from the device that generated the serialized data.